moore's_law (3)

So Much for Moore...

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Figure 1: Planar transistors vs finFETs vs nanosheet FET. Source: Samsung

 

Topics: Applied Physics, Electrical Engineering, Moore's Law, Nanotechnology, Semiconductor Technology


So much for the Moore's law limit. Although under current circumstances, the progression might be stalled by our current viral situation: the cost of chips will go higher, and consumers are currently making choices on food, jobs and toilet paper, not gadgets.

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that.

Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issues and the unforeseen pandemic outbreak, according to analysts. COVID-19 has slowed the momentum and impacted the sales in the IC industry.

This, in turn, is likely to push back the roadmaps beyond 3nm. Nevertheless, the current climate hasn’t stopped the semiconductor industry. Today, foundries and memory makers are running at relatively high fab utilization rates.

Behind the scenes, meanwhile, foundries and their customers continue to develop their 3nm and 2nm technologies, which are now slated for roughly 2022 and 2024, respectively. Work is also underway for 1nm and beyond, but that’s still far away.

Starting at 3nm, the industry hopes to make the transition from today’s finFET transistors to gate-all-around FETs. At 2nm and perhaps beyond, the industry is looking at current and new versions of gate-all-around transistors.

At these nodes, chipmakers will likely require new equipment, such as the next version of extreme ultraviolet (EUV) lithography. New deposition, etch and inspection/metrology technologies are also in the works.

Needless to say, the design and manufacturing costs are astronomical here. The design cost for a 3nm chip is $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, according to IBS. Beyond those nodes, it’s too early to say how much a chip will cost.

 

Making Chips At 3nm And Beyond
Mark Lapedus and Ed Sperling, Semiconductor Engineering

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Moore's Reckoning...

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Wiki Chip: 14 nm lithography process

 

Topics: Electrical Engineering, Moore's Law, Nanotechnology, Semiconductor Technology


It was hard to tell at the time — with the distraction of the Y2K bug, the explosion of reality television, and the popularity of post-grunge music — that the turn of the millennium was also the beginning of the end of easy computing improvements. A golden age of computing, which powered intensive data and computational science for decades, would soon be slowly drawing to a close. Even with novel ways of assembling computing systems, and new algorithms that take advantage of the architecture, the performance gains as predicted by Moore’s law were bound to come to an end — but in a way few people expected.

Moore’s law is the observation that the number of transistors in dense integrated circuits doubles roughly every two years. Before the turn of the millennium, all a computational scientist needed to do to have more than twice as fast a computer was to wait two years. Calculations that would have been impractical became accessible to desktop users. It was a time of plenty, and many problems could be solved by brute-force computing, from the quantum interactions of particles to the formation of galaxies. Giant lattices could be modeled, and enormous numbers of particles tracked. Improved computers enabled the analysis of genomic variations in entire communities and facilitated the advent of machine-learning techniques in AI.

Fundamental physics limits will ultimately put an end to transistor shrinkage in Moore’s law, and we are close to getting there. Today, chip production creates structures in silicon that are 14 nanometers wide and decreasing, and seven-nanometer elements are coming to market. At these sizes, thousands of these elements would fit in the width of a human hair. Feature sizes of less than five nanometers will probably be impossible because of quantum tunneling, in which electrons undesirably leak out of such narrow gaps.

 

A Reckoning for Moore’s Law
Why upgrading your computer every two years no longer makes sense.
Ian Fisk, Simon's Foundation

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Smart Packaging...

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Cheaper flexible integrated circuits open up new markets. (Courtesy: PragmatIC)

 

Topics: Applied Physics, Moore's Law, Semiconductor Technology, Nanotechnology


For more than 50 years, progress in the electronics industry has been guided by Moore’s law: the idea that the number of transistors in a silicon-based integrated circuit (IC) will double approximately every 18 months. The consequences of this doubling include a continual reduction in the size of silicon ICs, as it becomes possible to provide increasingly complex and high-performance functionality in smaller and smaller areas of silicon, and at progressively lower cost relative to the circuits’ processing power.

Moore’s law is an empirical rule of thumb rather than a robust physical principle, and much has been written about how, why and when it will eventually fail. But even before we reach that point, manufacturers are already finding that, in practice, the cost savings associated with reducing the size, or “footprint”, of ICs will only carry them so far. The reason is that below a certain minimum size, ICs become difficult to handle easily or effectively. For highly complex circuitry, such as that found in computers with many millions of transistors in a single IC, this limit on handling size may not be a consideration. However, for applications that require less complex circuits, the size constraint imposed by the physical aspect of handling ICs becomes a limiting factor in their cost.

The approach we have taken at PragmatIC is to use thin, flexible substrates, rather than rigid silicon, as the base for building our circuits. The low cost of the materials involved and the relatively low complexity of our target applications alters the economics around circuit footprint and overall IC cost. Accepting a larger footprint can lower capital expenditure because it means that ultrahigh-end precision tooling is not required to fabricate our circuits during the manufacturing process. In turn, for low-complexity applications, this can lead to a lower final IC cost.

The resulting flexible integrated circuits, or FlexICs, are thinner than a human hair, so they can easily be embedded in everyday objects. They also cost around 10 times less than silicon ICs, making it economically viable for them to appear in trillions of smart objects that engage with consumers and their environments. Since the technology was developed, PragmatIC FlexICs have been trialed in a wide variety of markets, including consumer goods, games, retail, and the pharmaceutical and security sectors.

 

A smart approach to smart packaging
Catherine Ramsdale is vice-president of device development at PragmatIC

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