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| Controlling magnetic clouds in graphene. Condensed Matter Physics Group, University of Manchester, UK |
A new way to grow high-quality, wafer-scale graphene measuring between 100 and 300 mm across has been developed by researchers in the US and UK. The feat is a major advance since a size of 300 mm represents the silicon wafer-scale standard and means that the carbon material might now be easily integrated with silicon – a major goal for graphene research.
Graphene, a sheet of carbon just one atom thick, is a promising material for making molecular electronic devices of the future thanks to its unique electronic and mechanical properties, which include extremely high electrical conductivity and exceptional strength. The first real-world applications of graphene devices will most likely involve combining the carbon material with silicon complementary metal-oxide-semiconductor (CMOS) technology. However, integrating graphene with Si CMOS has proved to be more difficult than first imagined since there is no reliable process capable of producing large-area graphene films that have the same high performance as chip-scale ones.
Researchers have already tried out several methods for growing wafer-scale graphene, including epitaxially growing the material on SiC wafers, reducing graphene oxide, chemical vapour deposition (CVD) on metal thin films (such as copper) and recently CVD on hydrogen-terminated single-crystalline germanium surfaces. Among these techniques, CVD is probably the best in terms of compatibility with Si very large-scale integrated (VLSI) technology. However, there is a problem in that the graphene produced can be quite defective and so suffers from lower charge carrier mobilities.
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| The aixtron 300 mm growth system. Courtesy: K Teo |
Now, a team of researchers led by Deji Akinwande of the University of Texas at Austin and Ken Teo of Aixtron Ltd in Cambridge, have grown CVD graphene films that measure between 100 and 300 mm across on polycrystalline copper films. The as-made polycrystalline graphene appears to have better charge carrier transport characteristics compared to previously synthesized poly- or single-crystalline wafers. What is more, the graphene covers over 96% of the substrates and has few defects – something that the researchers confirmed using a technique called Raman mapping.
Nano Tech Web: Graphene almost there for silicon wafer-scale standard
Belle Dumé, contributing editor at nanotechweb.org
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