Source: Semiengineering dot com - Chiplets

Topics: Computer Science, Electrical Engineering, Materials Science, Semiconductor Technology, Solid-State Physics

Depending on who you’re speaking with at the time, the industry’s adoption of chiplet technology to extend the reach of Moore’s Law is either continuing to roll along or is facing the absence of a commercial market. However, both assertions cannot be true. What is true is that chiplets have been used to build at least some commercial ICs for more than a decade and that semiconductor vendors continue to expand chiplet usability and availability. At the same time, the interface and packaging standards that are essential to widespread chiplet adoption remain in flux.

On the positive side of this question are existence proofs. Xilinx, now AMD, has been using 2.5D chiplet technology with large silicon interposers to make FPGAs for more than a decade. The first commercial use of this packaging technology appeared back in 2011 when Xilinx announced its Virtex-7 2000T FPGA, a 2-Mgate device built from four FPGA semiconductor tiles bonded to a silicon interposer. Xilinx jointly developed this chiplet-packaging technology with its foundry, TSMC, which now offers this CoWoS (Chip-on-Wafer-on-Substrate) interposer-and-chiplet technology to its other foundry customers. TSMC customers that have announced chiplet-based products include Broadcom and Fujitsu. AMD is now five generations along the learning curve with this packaging technology, which is now essential to the continued development of bigger and more diverse FPGAs. AMD will be presenting an overview of this multi-generation, chiplet-based technology, including a status update at the upcoming Hot Chips 2023 conference being held at Stanford University in Palo Alto, California, in August.

Similarly, Intel has long been developing and using chiplet technology in its own packaged ICs. The company has been using its 2.5D EMIB (embedded multi-die interconnect bridge) chiplet-packaging technology for years to manufacture its Stratix 10 FPGAs. That technology has now spread throughout Intel’s product line to include CPUs and SoCs. The poster child for Intel’s chiplet-packaging technologies is unquestionably the company’s Ponte Vecchio GPU, which packages 47 active “tiles” – Intel’s name for chiplets – in a multi-chip package. These 47 dies are manufactured by multiple semiconductor vendors using five different semiconductor process nodes, all combined in one package using Intel’s EMIB 2.5D and 3D Foveros chiplet-packaging techniques to produce an integrated product with more than 100 billion transistors – something not currently possible on one silicon die. Intel is now opening these chiplet-packaging technologies to select customers through IFS – Intel Foundry Services – and consequently expanding the size and number of its packaging facilities.

The Chiplet’s Time Is Coming. It’s Here, Or Not. Steven Leibson, Tirias Research, Forbes

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